Highly Scalable Multiplier(HSM) uses a folding technique to allow one to trade off speed, power dissipation, and area as needed in the implementation of multipliers. A multiplier is an important and essential building block in digital signal processing. The presently available multipliers are not scalable and consume significant amount of power. Dr. Shankar has received one patent, with three more in the pipeline. FAU has funded his preliminary work with a $15,000 grant (PI: Shankar, Co-PI: Agarwal) to map it to an FPGA to explore commercialization possibilities. Andrew Katan is working on his MS thesis addressing this topic.
Patent
 
Cool-Chip: A Power Saver for the Mobile Market R. Shankar
 

 
Other HSM Patents From Dr. Shankar

A Dynamically Reconfigurable Power-Aware, Highly Scalable Multiplier with Reusable and Logically Optimized Structures

High Speed Scalable Multiplier